linux-aarch32-low.cc 8.0 KB

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  1. /* Copyright (C) 1995-2022 Free Software Foundation, Inc.
  2. This file is part of GDB.
  3. This program is free software; you can redistribute it and/or modify
  4. it under the terms of the GNU General Public License as published by
  5. the Free Software Foundation; either version 3 of the License, or
  6. (at your option) any later version.
  7. This program is distributed in the hope that it will be useful,
  8. but WITHOUT ANY WARRANTY; without even the implied warranty of
  9. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  10. GNU General Public License for more details.
  11. You should have received a copy of the GNU General Public License
  12. along with this program. If not, see <http://www.gnu.org/licenses/>. */
  13. #include "server.h"
  14. #include "arch/arm.h"
  15. #include "arch/arm-linux.h"
  16. #include "linux-low.h"
  17. #include "linux-aarch32-low.h"
  18. #include <sys/ptrace.h>
  19. /* Don't include elf.h if linux/elf.h got included by gdb_proc_service.h.
  20. On Bionic elf.h and linux/elf.h have conflicting definitions. */
  21. #ifndef ELFMAG0
  22. #include <elf.h>
  23. #endif
  24. /* Correct in either endianness. */
  25. #define arm_abi_breakpoint 0xef9f0001UL
  26. /* For new EABI binaries. We recognize it regardless of which ABI
  27. is used for gdbserver, so single threaded debugging should work
  28. OK, but for multi-threaded debugging we only insert the current
  29. ABI's breakpoint instruction. For now at least. */
  30. #define arm_eabi_breakpoint 0xe7f001f0UL
  31. #if (defined __ARM_EABI__ || defined __aarch64__)
  32. static const unsigned long arm_breakpoint = arm_eabi_breakpoint;
  33. #else
  34. static const unsigned long arm_breakpoint = arm_abi_breakpoint;
  35. #endif
  36. #define arm_breakpoint_len 4
  37. static const unsigned short thumb_breakpoint = 0xde01;
  38. #define thumb_breakpoint_len 2
  39. static const unsigned short thumb2_breakpoint[] = { 0xf7f0, 0xa000 };
  40. #define thumb2_breakpoint_len 4
  41. /* Some older versions of GNU/Linux and Android do not define
  42. the following macros. */
  43. #ifndef NT_ARM_VFP
  44. #define NT_ARM_VFP 0x400
  45. #endif
  46. /* Collect GP registers from REGCACHE to buffer BUF. */
  47. void
  48. arm_fill_gregset (struct regcache *regcache, void *buf)
  49. {
  50. int i;
  51. uint32_t *regs = (uint32_t *) buf;
  52. uint32_t cpsr = regs[ARM_CPSR_GREGNUM];
  53. for (i = ARM_A1_REGNUM; i <= ARM_PC_REGNUM; i++)
  54. collect_register (regcache, i, &regs[i]);
  55. collect_register (regcache, ARM_PS_REGNUM, &regs[ARM_CPSR_GREGNUM]);
  56. /* Keep reserved bits bit 20 to bit 23. */
  57. regs[ARM_CPSR_GREGNUM] = ((regs[ARM_CPSR_GREGNUM] & 0xff0fffff)
  58. | (cpsr & 0x00f00000));
  59. }
  60. /* Supply GP registers contents, stored in BUF, to REGCACHE. */
  61. void
  62. arm_store_gregset (struct regcache *regcache, const void *buf)
  63. {
  64. int i;
  65. char zerobuf[8];
  66. const uint32_t *regs = (const uint32_t *) buf;
  67. uint32_t cpsr = regs[ARM_CPSR_GREGNUM];
  68. memset (zerobuf, 0, 8);
  69. for (i = ARM_A1_REGNUM; i <= ARM_PC_REGNUM; i++)
  70. supply_register (regcache, i, &regs[i]);
  71. for (; i < ARM_PS_REGNUM; i++)
  72. supply_register (regcache, i, zerobuf);
  73. /* Clear reserved bits bit 20 to bit 23. */
  74. cpsr &= 0xff0fffff;
  75. supply_register (regcache, ARM_PS_REGNUM, &cpsr);
  76. }
  77. /* Collect NUM number of VFP registers from REGCACHE to buffer BUF. */
  78. void
  79. arm_fill_vfpregset_num (struct regcache *regcache, void *buf, int num)
  80. {
  81. int i, base;
  82. gdb_assert (num == 16 || num == 32);
  83. base = find_regno (regcache->tdesc, "d0");
  84. for (i = 0; i < num; i++)
  85. collect_register (regcache, base + i, (char *) buf + i * 8);
  86. collect_register_by_name (regcache, "fpscr", (char *) buf + 32 * 8);
  87. }
  88. /* Supply NUM number of VFP registers contents, stored in BUF, to
  89. REGCACHE. */
  90. void
  91. arm_store_vfpregset_num (struct regcache *regcache, const void *buf, int num)
  92. {
  93. int i, base;
  94. gdb_assert (num == 16 || num == 32);
  95. base = find_regno (regcache->tdesc, "d0");
  96. for (i = 0; i < num; i++)
  97. supply_register (regcache, base + i, (char *) buf + i * 8);
  98. supply_register_by_name (regcache, "fpscr", (char *) buf + 32 * 8);
  99. }
  100. static void
  101. arm_fill_vfpregset (struct regcache *regcache, void *buf)
  102. {
  103. arm_fill_vfpregset_num (regcache, buf, 32);
  104. }
  105. static void
  106. arm_store_vfpregset (struct regcache *regcache, const void *buf)
  107. {
  108. arm_store_vfpregset_num (regcache, buf, 32);
  109. }
  110. /* Register sets with using PTRACE_GETREGSET. */
  111. static struct regset_info aarch32_regsets[] = {
  112. { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_PRSTATUS,
  113. ARM_CORE_REGS_SIZE + ARM_INT_REGISTER_SIZE, GENERAL_REGS,
  114. arm_fill_gregset, arm_store_gregset },
  115. { PTRACE_GETREGSET, PTRACE_SETREGSET, NT_ARM_VFP, ARM_VFP3_REGS_SIZE,
  116. EXTENDED_REGS,
  117. arm_fill_vfpregset, arm_store_vfpregset },
  118. NULL_REGSET
  119. };
  120. static struct regsets_info aarch32_regsets_info =
  121. {
  122. aarch32_regsets, /* regsets */
  123. 0, /* num_regsets */
  124. NULL, /* disabled_regsets */
  125. };
  126. struct regs_info regs_info_aarch32 =
  127. {
  128. NULL, /* regset_bitmap */
  129. NULL, /* usrregs */
  130. &aarch32_regsets_info
  131. };
  132. /* Returns 1 if the current instruction set is thumb, 0 otherwise. */
  133. int
  134. arm_is_thumb_mode (void)
  135. {
  136. struct regcache *regcache = get_thread_regcache (current_thread, 1);
  137. unsigned long cpsr;
  138. collect_register_by_name (regcache, "cpsr", &cpsr);
  139. if (cpsr & 0x20)
  140. return 1;
  141. else
  142. return 0;
  143. }
  144. /* Returns 1 if there is a software breakpoint at location. */
  145. int
  146. arm_breakpoint_at (CORE_ADDR where)
  147. {
  148. if (arm_is_thumb_mode ())
  149. {
  150. /* Thumb mode. */
  151. unsigned short insn;
  152. the_target->read_memory (where, (unsigned char *) &insn, 2);
  153. if (insn == thumb_breakpoint)
  154. return 1;
  155. if (insn == thumb2_breakpoint[0])
  156. {
  157. the_target->read_memory (where + 2, (unsigned char *) &insn, 2);
  158. if (insn == thumb2_breakpoint[1])
  159. return 1;
  160. }
  161. }
  162. else
  163. {
  164. /* ARM mode. */
  165. unsigned long insn;
  166. the_target->read_memory (where, (unsigned char *) &insn, 4);
  167. if (insn == arm_abi_breakpoint)
  168. return 1;
  169. if (insn == arm_eabi_breakpoint)
  170. return 1;
  171. }
  172. return 0;
  173. }
  174. /* Implementation of linux_target_ops method "breakpoint_kind_from_pc".
  175. Determine the type and size of breakpoint to insert at PCPTR. Uses the
  176. program counter value to determine whether a 16-bit or 32-bit breakpoint
  177. should be used. It returns the breakpoint's kind, and adjusts the program
  178. counter (if necessary) to point to the actual memory location where the
  179. breakpoint should be inserted. */
  180. int
  181. arm_breakpoint_kind_from_pc (CORE_ADDR *pcptr)
  182. {
  183. if (IS_THUMB_ADDR (*pcptr))
  184. {
  185. gdb_byte buf[2];
  186. *pcptr = UNMAKE_THUMB_ADDR (*pcptr);
  187. /* Check whether we are replacing a thumb2 32-bit instruction. */
  188. if (target_read_memory (*pcptr, buf, 2) == 0)
  189. {
  190. unsigned short inst1 = 0;
  191. target_read_memory (*pcptr, (gdb_byte *) &inst1, 2);
  192. if (thumb_insn_size (inst1) == 4)
  193. return ARM_BP_KIND_THUMB2;
  194. }
  195. return ARM_BP_KIND_THUMB;
  196. }
  197. else
  198. return ARM_BP_KIND_ARM;
  199. }
  200. /* Implementation of the linux_target_ops method "sw_breakpoint_from_kind". */
  201. const gdb_byte *
  202. arm_sw_breakpoint_from_kind (int kind , int *size)
  203. {
  204. *size = arm_breakpoint_len;
  205. /* Define an ARM-mode breakpoint; we only set breakpoints in the C
  206. library, which is most likely to be ARM. If the kernel supports
  207. clone events, we will never insert a breakpoint, so even a Thumb
  208. C library will work; so will mixing EABI/non-EABI gdbserver and
  209. application. */
  210. switch (kind)
  211. {
  212. case ARM_BP_KIND_THUMB:
  213. *size = thumb_breakpoint_len;
  214. return (gdb_byte *) &thumb_breakpoint;
  215. case ARM_BP_KIND_THUMB2:
  216. *size = thumb2_breakpoint_len;
  217. return (gdb_byte *) &thumb2_breakpoint;
  218. case ARM_BP_KIND_ARM:
  219. *size = arm_breakpoint_len;
  220. return (const gdb_byte *) &arm_breakpoint;
  221. default:
  222. return NULL;
  223. }
  224. return NULL;
  225. }
  226. /* Implementation of the linux_target_ops method
  227. "breakpoint_kind_from_current_state". */
  228. int
  229. arm_breakpoint_kind_from_current_state (CORE_ADDR *pcptr)
  230. {
  231. if (arm_is_thumb_mode ())
  232. {
  233. *pcptr = MAKE_THUMB_ADDR (*pcptr);
  234. return arm_breakpoint_kind_from_pc (pcptr);
  235. }
  236. else
  237. {
  238. return arm_breakpoint_kind_from_pc (pcptr);
  239. }
  240. }
  241. void
  242. initialize_low_arch_aarch32 (void)
  243. {
  244. initialize_regsets_info (&aarch32_regsets_info);
  245. }