riscv-tdep.h 6.9 KB

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  1. /* Target-dependent header for the RISC-V architecture, for GDB, the
  2. GNU Debugger.
  3. Copyright (C) 2018-2022 Free Software Foundation, Inc.
  4. This file is part of GDB.
  5. This program is free software; you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation; either version 3 of the License, or
  8. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. GNU General Public License for more details.
  13. You should have received a copy of the GNU General Public License
  14. along with this program. If not, see <http://www.gnu.org/licenses/>. */
  15. #ifndef RISCV_TDEP_H
  16. #define RISCV_TDEP_H
  17. #include "arch/riscv.h"
  18. #include "gdbarch.h"
  19. /* RiscV register numbers. */
  20. enum
  21. {
  22. RISCV_ZERO_REGNUM = 0, /* Read-only register, always 0. */
  23. RISCV_RA_REGNUM = 1, /* Return Address. */
  24. RISCV_SP_REGNUM = 2, /* Stack Pointer. */
  25. RISCV_GP_REGNUM = 3, /* Global Pointer. */
  26. RISCV_TP_REGNUM = 4, /* Thread Pointer. */
  27. RISCV_FP_REGNUM = 8, /* Frame Pointer. */
  28. RISCV_A0_REGNUM = 10, /* First argument. */
  29. RISCV_A1_REGNUM = 11, /* Second argument. */
  30. RISCV_A7_REGNUM = 17, /* Seventh argument. */
  31. RISCV_PC_REGNUM = 32, /* Program Counter. */
  32. RISCV_NUM_INTEGER_REGS = 32,
  33. RISCV_FIRST_FP_REGNUM = 33, /* First Floating Point Register */
  34. RISCV_FA0_REGNUM = 43,
  35. RISCV_FA1_REGNUM = RISCV_FA0_REGNUM + 1,
  36. RISCV_LAST_FP_REGNUM = 64, /* Last Floating Point Register */
  37. RISCV_FIRST_CSR_REGNUM = 65, /* First CSR */
  38. #define DECLARE_CSR(name, num, class, define_version, abort_version) \
  39. RISCV_ ## num ## _REGNUM = RISCV_FIRST_CSR_REGNUM + num,
  40. #include "opcode/riscv-opc.h"
  41. #undef DECLARE_CSR
  42. RISCV_LAST_CSR_REGNUM = 4160,
  43. RISCV_CSR_LEGACY_MISA_REGNUM = 0xf10 + RISCV_FIRST_CSR_REGNUM,
  44. RISCV_PRIV_REGNUM = 4161,
  45. RISCV_V0_REGNUM,
  46. RISCV_V31_REGNUM = RISCV_V0_REGNUM + 31,
  47. RISCV_LAST_REGNUM = RISCV_V31_REGNUM
  48. };
  49. /* RiscV DWARF register numbers. */
  50. enum
  51. {
  52. RISCV_DWARF_REGNUM_X0 = 0,
  53. RISCV_DWARF_REGNUM_X31 = 31,
  54. RISCV_DWARF_REGNUM_F0 = 32,
  55. RISCV_DWARF_REGNUM_F31 = 63,
  56. RISCV_DWARF_REGNUM_V0 = 96,
  57. RISCV_DWARF_REGNUM_V31 = 127,
  58. RISCV_DWARF_FIRST_CSR = 4096,
  59. RISCV_DWARF_LAST_CSR = 8191,
  60. };
  61. /* RISC-V specific per-architecture information. */
  62. struct riscv_gdbarch_tdep : gdbarch_tdep
  63. {
  64. /* Features about the target hardware that impact how the gdbarch is
  65. configured. Two gdbarch instances are compatible only if this field
  66. matches. */
  67. struct riscv_gdbarch_features isa_features;
  68. /* Features about the abi that impact how the gdbarch is configured. Two
  69. gdbarch instances are compatible only if this field matches. */
  70. struct riscv_gdbarch_features abi_features;
  71. /* ISA-specific data types. */
  72. struct type *riscv_fpreg_d_type = nullptr;
  73. /* Use for tracking unknown CSRs in the target description.
  74. UNKNOWN_CSRS_FIRST_REGNUM is the number assigned to the first unknown
  75. CSR. All other unknown CSRs will be assigned sequential numbers after
  76. this, with UNKNOWN_CSRS_COUNT being the total number of unknown CSRs. */
  77. int unknown_csrs_first_regnum = -1;
  78. int unknown_csrs_count = 0;
  79. /* Some targets (QEMU) are reporting three registers twice in the target
  80. description they send. These three register numbers, when not set to
  81. -1, are for the duplicate copies of these registers. */
  82. int duplicate_fflags_regnum = -1;
  83. int duplicate_frm_regnum = -1;
  84. int duplicate_fcsr_regnum = -1;
  85. /* Return the expected next PC assuming FRAME is stopped at a syscall
  86. instruction. */
  87. CORE_ADDR (*syscall_next_pc) (struct frame_info *frame) = nullptr;
  88. };
  89. /* Return the width in bytes of the general purpose registers for GDBARCH.
  90. Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or
  91. RV128. */
  92. extern int riscv_isa_xlen (struct gdbarch *gdbarch);
  93. /* Return the width in bytes of the hardware floating point registers for
  94. GDBARCH. If this architecture has no floating point registers, then
  95. return 0. Possible values are 4, 8, or 16 for depending on which of
  96. single, double or quad floating point support is available. */
  97. extern int riscv_isa_flen (struct gdbarch *gdbarch);
  98. /* Return the width in bytes of the general purpose register abi for
  99. GDBARCH. This can be equal to, or less than RISCV_ISA_XLEN and reflects
  100. how the binary was compiled rather than the hardware that is available.
  101. It is possible that a binary compiled for RV32 is being run on an RV64
  102. target, in which case the isa xlen is 8-bytes, and the abi xlen is
  103. 4-bytes. This will impact how inferior functions are called. */
  104. extern int riscv_abi_xlen (struct gdbarch *gdbarch);
  105. /* Return the width in bytes of the floating point register abi for
  106. GDBARCH. This reflects how the binary was compiled rather than the
  107. hardware that is available. It is possible that a binary is compiled
  108. for single precision floating point, and then run on a target with
  109. double precision floating point. A return value of 0 indicates that no
  110. floating point abi is in use (floating point arguments will be passed
  111. in integer registers) other possible return value are 4, 8, or 16 as
  112. with RISCV_ISA_FLEN. */
  113. extern int riscv_abi_flen (struct gdbarch *gdbarch);
  114. /* Return true if GDBARCH is using the embedded x-regs abi, that is the
  115. target only has 16 x-registers, which includes a reduced number of
  116. argument registers. */
  117. extern bool riscv_abi_embedded (struct gdbarch *gdbarch);
  118. /* Single step based on where the current instruction will take us. */
  119. extern std::vector<CORE_ADDR> riscv_software_single_step
  120. (struct regcache *regcache);
  121. /* Supply register REGNUM from the buffer REGS (length LEN) into
  122. REGCACHE. REGSET describes the layout of the buffer. If REGNUM is -1
  123. then all registers described by REGSET are supplied.
  124. The register RISCV_ZERO_REGNUM should not be described by REGSET,
  125. however, this register (which always has the value 0) will be supplied
  126. by this function if requested.
  127. The registers RISCV_CSR_FFLAGS_REGNUM and RISCV_CSR_FRM_REGNUM should
  128. not be described by REGSET, however, these register will be provided if
  129. requested assuming either:
  130. (a) REGCACHE already contains the value of RISCV_CSR_FCSR_REGNUM, or
  131. (b) REGSET describes the location of RISCV_CSR_FCSR_REGNUM in the REGS
  132. buffer.
  133. This function can be used as the supply function for either x-regs or
  134. f-regs when loading corefiles, and doesn't care which abi is currently
  135. in use. */
  136. extern void riscv_supply_regset (const struct regset *regset,
  137. struct regcache *regcache, int regnum,
  138. const void *regs, size_t len);
  139. /* The names of the RISC-V target description features. */
  140. extern const char *riscv_feature_name_csr;
  141. #endif /* RISCV_TDEP_H */