arm-linux.c 4.0 KB

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  1. /* Common target dependent code for GNU/Linux on ARM systems.
  2. Copyright (C) 1999-2022 Free Software Foundation, Inc.
  3. This file is part of GDB.
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 3 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program. If not, see <http://www.gnu.org/licenses/>. */
  14. #include "gdbsupport/common-defs.h"
  15. #include "gdbsupport/common-regcache.h"
  16. #include "arch/arm.h"
  17. #include "arm-linux.h"
  18. #include "arch/arm-get-next-pcs.h"
  19. /* Calculate the offset from stack pointer of the pc register on the stack
  20. in the case of a sigreturn or sigreturn_rt syscall. */
  21. int
  22. arm_linux_sigreturn_next_pc_offset (unsigned long sp,
  23. unsigned long sp_data,
  24. unsigned long svc_number,
  25. int is_sigreturn)
  26. {
  27. /* Offset of R0 register. */
  28. int r0_offset = 0;
  29. /* Offset of PC register. */
  30. int pc_offset = 0;
  31. if (is_sigreturn)
  32. {
  33. if (sp_data == ARM_NEW_SIGFRAME_MAGIC)
  34. r0_offset = ARM_UCONTEXT_SIGCONTEXT + ARM_SIGCONTEXT_R0;
  35. else
  36. r0_offset = ARM_SIGCONTEXT_R0;
  37. }
  38. else
  39. {
  40. if (sp_data == sp + ARM_OLD_RT_SIGFRAME_SIGINFO)
  41. r0_offset = ARM_OLD_RT_SIGFRAME_UCONTEXT;
  42. else
  43. r0_offset = ARM_NEW_RT_SIGFRAME_UCONTEXT;
  44. r0_offset += ARM_UCONTEXT_SIGCONTEXT + ARM_SIGCONTEXT_R0;
  45. }
  46. pc_offset = r0_offset + ARM_INT_REGISTER_SIZE * ARM_PC_REGNUM;
  47. return pc_offset;
  48. }
  49. /* Implementation of "fixup" method of struct arm_get_next_pcs_ops
  50. for arm-linux. */
  51. CORE_ADDR
  52. arm_linux_get_next_pcs_fixup (struct arm_get_next_pcs *self,
  53. CORE_ADDR nextpc)
  54. {
  55. /* The Linux kernel offers some user-mode helpers in a high page. We can
  56. not read this page (as of 2.6.23), and even if we could then we
  57. couldn't set breakpoints in it, and even if we could then the atomic
  58. operations would fail when interrupted. They are all (tail) called
  59. as functions and return to the address in LR. However, when GDB single
  60. step this instruction, this instruction isn't executed yet, and LR
  61. may not be updated yet. In other words, GDB can get the target
  62. address from LR if this instruction isn't BL or BLX. */
  63. if (nextpc > 0xffff0000)
  64. {
  65. int bl_blx_p = 0;
  66. CORE_ADDR pc = regcache_read_pc (self->regcache);
  67. int pc_incr = 0;
  68. if (self->ops->is_thumb (self))
  69. {
  70. unsigned short inst1
  71. = self->ops->read_mem_uint (pc, 2, self->byte_order_for_code);
  72. if (bits (inst1, 8, 15) == 0x47 && bit (inst1, 7))
  73. {
  74. /* BLX Rm */
  75. bl_blx_p = 1;
  76. pc_incr = 2;
  77. }
  78. else if (thumb_insn_size (inst1) == 4)
  79. {
  80. unsigned short inst2;
  81. inst2 = self->ops->read_mem_uint (pc + 2, 2,
  82. self->byte_order_for_code);
  83. if ((inst1 & 0xf800) == 0xf000 && bits (inst2, 14, 15) == 0x3)
  84. {
  85. /* BL <label> and BLX <label> */
  86. bl_blx_p = 1;
  87. pc_incr = 4;
  88. }
  89. }
  90. pc_incr = MAKE_THUMB_ADDR (pc_incr);
  91. }
  92. else
  93. {
  94. unsigned int insn
  95. = self->ops->read_mem_uint (pc, 4, self->byte_order_for_code);
  96. if (bits (insn, 28, 31) == INST_NV)
  97. {
  98. if (bits (insn, 25, 27) == 0x5) /* BLX <label> */
  99. bl_blx_p = 1;
  100. }
  101. else
  102. {
  103. if (bits (insn, 24, 27) == 0xb /* BL <label> */
  104. || bits (insn, 4, 27) == 0x12fff3 /* BLX Rm */)
  105. bl_blx_p = 1;
  106. }
  107. pc_incr = 4;
  108. }
  109. /* If the instruction BL or BLX, the target address is the following
  110. instruction of BL or BLX, otherwise, the target address is in LR
  111. already. */
  112. if (bl_blx_p)
  113. nextpc = pc + pc_incr;
  114. else
  115. nextpc = regcache_raw_get_unsigned (self->regcache, ARM_LR_REGNUM);
  116. }
  117. return nextpc;
  118. }