aarch64-nat.c 8.9 KB

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  1. /* Native-dependent code for AArch64.
  2. Copyright (C) 2011-2022 Free Software Foundation, Inc.
  3. This file is part of GDB.
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 3 of the License, or
  7. (at your option) any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program. If not, see <http://www.gnu.org/licenses/>. */
  14. #include "defs.h"
  15. #include "gdbarch.h"
  16. #include "inferior.h"
  17. #include "cli/cli-cmds.h"
  18. #include "aarch64-nat.h"
  19. #include <unordered_map>
  20. /* Hash table storing per-process data. We don't bind this to a
  21. per-inferior registry because of targets like x86 GNU/Linux that
  22. need to keep track of processes that aren't bound to any inferior
  23. (e.g., fork children, checkpoints). */
  24. static std::unordered_map<pid_t, aarch64_debug_reg_state>
  25. aarch64_debug_process_state;
  26. /* See aarch64-nat.h. */
  27. struct aarch64_debug_reg_state *
  28. aarch64_lookup_debug_reg_state (pid_t pid)
  29. {
  30. auto it = aarch64_debug_process_state.find (pid);
  31. if (it != aarch64_debug_process_state.end ())
  32. return &it->second;
  33. return nullptr;
  34. }
  35. /* See aarch64-nat.h. */
  36. struct aarch64_debug_reg_state *
  37. aarch64_get_debug_reg_state (pid_t pid)
  38. {
  39. return &aarch64_debug_process_state[pid];
  40. }
  41. /* See aarch64-nat.h. */
  42. void
  43. aarch64_remove_debug_reg_state (pid_t pid)
  44. {
  45. aarch64_debug_process_state.erase (pid);
  46. }
  47. /* Returns the number of hardware watchpoints of type TYPE that we can
  48. set. Value is positive if we can set CNT watchpoints, zero if
  49. setting watchpoints of type TYPE is not supported, and negative if
  50. CNT is more than the maximum number of watchpoints of type TYPE
  51. that we can support. TYPE is one of bp_hardware_watchpoint,
  52. bp_read_watchpoint, bp_write_watchpoint, or bp_hardware_breakpoint.
  53. CNT is the number of such watchpoints used so far (including this
  54. one). OTHERTYPE is non-zero if other types of watchpoints are
  55. currently enabled. */
  56. int
  57. aarch64_can_use_hw_breakpoint (enum bptype type, int cnt, int othertype)
  58. {
  59. if (type == bp_hardware_watchpoint || type == bp_read_watchpoint
  60. || type == bp_access_watchpoint || type == bp_watchpoint)
  61. {
  62. if (aarch64_num_wp_regs == 0)
  63. return 0;
  64. }
  65. else if (type == bp_hardware_breakpoint)
  66. {
  67. if (aarch64_num_bp_regs == 0)
  68. return 0;
  69. }
  70. else
  71. gdb_assert_not_reached ("unexpected breakpoint type");
  72. /* We always return 1 here because we don't have enough information
  73. about possible overlap of addresses that they want to watch. As an
  74. extreme example, consider the case where all the watchpoints watch
  75. the same address and the same region length: then we can handle a
  76. virtually unlimited number of watchpoints, due to debug register
  77. sharing implemented via reference counts. */
  78. return 1;
  79. }
  80. /* Insert a hardware-assisted breakpoint at BP_TGT->reqstd_address.
  81. Return 0 on success, -1 on failure. */
  82. int
  83. aarch64_insert_hw_breakpoint (struct gdbarch *gdbarch,
  84. struct bp_target_info *bp_tgt)
  85. {
  86. int ret;
  87. CORE_ADDR addr = bp_tgt->placed_address = bp_tgt->reqstd_address;
  88. int len;
  89. const enum target_hw_bp_type type = hw_execute;
  90. struct aarch64_debug_reg_state *state
  91. = aarch64_get_debug_reg_state (inferior_ptid.pid ());
  92. gdbarch_breakpoint_from_pc (gdbarch, &addr, &len);
  93. if (show_debug_regs)
  94. gdb_printf (gdb_stdlog,
  95. "insert_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n",
  96. (unsigned long) addr, len);
  97. ret = aarch64_handle_breakpoint (type, addr, len, 1 /* is_insert */,
  98. inferior_ptid, state);
  99. if (show_debug_regs)
  100. {
  101. aarch64_show_debug_reg_state (state,
  102. "insert_hw_breakpoint", addr, len, type);
  103. }
  104. return ret;
  105. }
  106. /* Remove a hardware-assisted breakpoint at BP_TGT->placed_address.
  107. Return 0 on success, -1 on failure. */
  108. int
  109. aarch64_remove_hw_breakpoint (struct gdbarch *gdbarch,
  110. struct bp_target_info *bp_tgt)
  111. {
  112. int ret;
  113. CORE_ADDR addr = bp_tgt->placed_address;
  114. int len = 4;
  115. const enum target_hw_bp_type type = hw_execute;
  116. struct aarch64_debug_reg_state *state
  117. = aarch64_get_debug_reg_state (inferior_ptid.pid ());
  118. gdbarch_breakpoint_from_pc (gdbarch, &addr, &len);
  119. if (show_debug_regs)
  120. gdb_printf (gdb_stdlog,
  121. "remove_hw_breakpoint on entry (addr=0x%08lx, len=%d))\n",
  122. (unsigned long) addr, len);
  123. ret = aarch64_handle_breakpoint (type, addr, len, 0 /* is_insert */,
  124. inferior_ptid, state);
  125. if (show_debug_regs)
  126. {
  127. aarch64_show_debug_reg_state (state,
  128. "remove_hw_watchpoint", addr, len, type);
  129. }
  130. return ret;
  131. }
  132. /* Insert a watchpoint to watch a memory region which starts at
  133. address ADDR and whose length is LEN bytes. Watch memory accesses
  134. of the type TYPE. Return 0 on success, -1 on failure. */
  135. int
  136. aarch64_insert_watchpoint (CORE_ADDR addr, int len, enum target_hw_bp_type type,
  137. struct expression *cond)
  138. {
  139. int ret;
  140. struct aarch64_debug_reg_state *state
  141. = aarch64_get_debug_reg_state (inferior_ptid.pid ());
  142. if (show_debug_regs)
  143. gdb_printf (gdb_stdlog,
  144. "insert_watchpoint on entry (addr=0x%08lx, len=%d)\n",
  145. (unsigned long) addr, len);
  146. gdb_assert (type != hw_execute);
  147. ret = aarch64_handle_watchpoint (type, addr, len, 1 /* is_insert */,
  148. inferior_ptid, state);
  149. if (show_debug_regs)
  150. {
  151. aarch64_show_debug_reg_state (state,
  152. "insert_watchpoint", addr, len, type);
  153. }
  154. return ret;
  155. }
  156. /* Remove a watchpoint that watched the memory region which starts at
  157. address ADDR, whose length is LEN bytes, and for accesses of the
  158. type TYPE. Return 0 on success, -1 on failure. */
  159. int
  160. aarch64_remove_watchpoint (CORE_ADDR addr, int len, enum target_hw_bp_type type,
  161. struct expression *cond)
  162. {
  163. int ret;
  164. struct aarch64_debug_reg_state *state
  165. = aarch64_get_debug_reg_state (inferior_ptid.pid ());
  166. if (show_debug_regs)
  167. gdb_printf (gdb_stdlog,
  168. "remove_watchpoint on entry (addr=0x%08lx, len=%d)\n",
  169. (unsigned long) addr, len);
  170. gdb_assert (type != hw_execute);
  171. ret = aarch64_handle_watchpoint (type, addr, len, 0 /* is_insert */,
  172. inferior_ptid, state);
  173. if (show_debug_regs)
  174. {
  175. aarch64_show_debug_reg_state (state,
  176. "remove_watchpoint", addr, len, type);
  177. }
  178. return ret;
  179. }
  180. /* See aarch64-nat.h. */
  181. bool
  182. aarch64_stopped_data_address (const struct aarch64_debug_reg_state *state,
  183. CORE_ADDR addr_trap, CORE_ADDR *addr_p)
  184. {
  185. int i;
  186. for (i = aarch64_num_wp_regs - 1; i >= 0; --i)
  187. {
  188. const unsigned int offset
  189. = aarch64_watchpoint_offset (state->dr_ctrl_wp[i]);
  190. const unsigned int len = aarch64_watchpoint_length (state->dr_ctrl_wp[i]);
  191. const CORE_ADDR addr_watch = state->dr_addr_wp[i] + offset;
  192. const CORE_ADDR addr_watch_aligned = align_down (state->dr_addr_wp[i], 8);
  193. const CORE_ADDR addr_orig = state->dr_addr_orig_wp[i];
  194. if (state->dr_ref_count_wp[i]
  195. && DR_CONTROL_ENABLED (state->dr_ctrl_wp[i])
  196. && addr_trap >= addr_watch_aligned
  197. && addr_trap < addr_watch + len)
  198. {
  199. /* ADDR_TRAP reports the first address of the memory range
  200. accessed by the CPU, regardless of what was the memory
  201. range watched. Thus, a large CPU access that straddles
  202. the ADDR_WATCH..ADDR_WATCH+LEN range may result in an
  203. ADDR_TRAP that is lower than the
  204. ADDR_WATCH..ADDR_WATCH+LEN range. E.g.:
  205. addr: | 4 | 5 | 6 | 7 | 8 |
  206. |---- range watched ----|
  207. |----------- range accessed ------------|
  208. In this case, ADDR_TRAP will be 4.
  209. To match a watchpoint known to GDB core, we must never
  210. report *ADDR_P outside of any ADDR_WATCH..ADDR_WATCH+LEN
  211. range. ADDR_WATCH <= ADDR_TRAP < ADDR_ORIG is a false
  212. positive on kernels older than 4.10. See PR
  213. external/20207. */
  214. *addr_p = addr_orig;
  215. return true;
  216. }
  217. }
  218. return false;
  219. }
  220. /* Define AArch64 maintenance commands. */
  221. static void
  222. add_show_debug_regs_command (void)
  223. {
  224. /* A maintenance command to enable printing the internal DRi mirror
  225. variables. */
  226. add_setshow_boolean_cmd ("show-debug-regs", class_maintenance,
  227. &show_debug_regs, _("\
  228. Set whether to show variables that mirror the AArch64 debug registers."), _("\
  229. Show whether to show variables that mirror the AArch64 debug registers."), _("\
  230. Use \"on\" to enable, \"off\" to disable.\n\
  231. If enabled, the debug registers values are shown when GDB inserts\n\
  232. or removes a hardware breakpoint or watchpoint, and when the inferior\n\
  233. triggers a breakpoint or watchpoint."),
  234. NULL,
  235. NULL,
  236. &maintenance_set_cmdlist,
  237. &maintenance_show_cmdlist);
  238. }
  239. void
  240. aarch64_initialize_hw_point ()
  241. {
  242. add_show_debug_regs_command ();
  243. }